Luiz André Barroso

      Luiz André Barroso

Publications

  1. Towards Energy Proportionality for Large-Scale Latency-Critical Workloads, David Lo, Liqun Cheng, Rama Govindaraju, Luiz André Barroso and Christos Kozyrakis. Proceedings of the 41st ACM International Symposium on Computer Architecture, Minneapolis, MN, June 2014.
  2. The Datacenter as a Computer - an introduction to the design of warehouse-scale machines - 2nd Edition, Luiz André Barroso, Jimmy Clidaras and Urs Hölzle. Synthesis Series on Computer Architecture, Morgan & Claypool Publishers, May 2013.
  3. The Tail at Scale, Jeffrey Dean and Luiz André Barroso, Communications of the ACM, Vol 56, Issue 2, February 2013.
  4. Technical Perspective on FAWN, a fast array of wimpy nodes, Luiz André Barroso, Communications of the ACM, Vol 54, Issue 7, July 2011.
  5. Power Management of Online Data-Intensive Services, David Meisner, Christopher M. Sadler, Luiz André Barroso, Wolf-Dietrich Weber and Thomas F. Wenisch. Proceedings of the 38th ACM International Symposium on Computer Architecture, San Jose, CA, June 2011.
  6. The Future of Computing Performance: Game Over or Next Level, National Academies Press, Samuel H. Fuller and Lynette I. Millet, Editors; Committee on Sustaning Growth in Computing Performance, National Research Council, 2011.
  7. Availability in Globally Distributed Storage Systems, Daniel Ford, Francois Labelle, Florentina Popovici, Murray Stokely, Van-Anh Truong, Luiz André Barroso, Carrie Grimes and Sean Quinlan. Proceedings of the 9th USENIX Symposium on Operating Systems Design and Implementation, Vancouver, Canada, October 2010.
  8. Dapper, a Large-Scale Distributed Systems Tracing Infrastructure, Benjamin H. Sigelman, Luiz André Barroso, Mike Burrows, Pat Stephenson, Manoj Plakal, Donald Beaver, Saul Jaspan and Chandan Shanbhag. Google Technical Report, April 2010.
  9. Internet Predictions: Warehouse Scale Computers, Urs Hölzle and Luiz André Barroso. Part of a collection of short essays co-edited by Vinton G. Cerf and Munindar P. Singh, IEEE Internet Computing, Jan/Feb 2010.
  10. The Datacenter as a Computer - an introduction to the design of warehouse-scale machines, Luiz André Barroso and Urs Hölzle. Synthesis Series on Computer Architecture, Morgan & Claypool Publishers, May 2009.
  11. The Case for Energy-Proportional Computing, Luiz André Barroso and Urs Hölzle. IEEE Computer, Vol. 40, No. 12, December 2007.
  12. Power Provisioning for a Warehouse-sized Computer, Xiaobo Fan, Wolf-Dietrich Weber and Luiz André Barroso. In Proceedings of the 34th ACM International Symposium on Computer Architecture, San Diego, CA, June 2007.
  13. Failure Trends in a Large Disk Drive Population, Eduardo Pinheiro, Wolf-Dietrich Weber and Luiz André Barroso. In Proceedings of the 5th USENIX Conference on File and Storage Technologies, San Jose, CA, Feb 2007.
  14. The Price of Performance: An Economic Case for Chip Multiprocessing, Luiz André Barroso. In ACM Queue, September 2005.
  15. Web Search for A Planet: The Architecture of the Google Cluster, Urs Hoelzle, Jeffrey Dean, and Luiz André Barroso. In IEEE Micro Magazine, April 2003.
  16. A Detailed Comparison of Two Transaction Processing Workloads, Robert Stets, Luiz André Barroso, and Kourosh Gharachorloo. In Proceedings of the IEEE 5th Annual Workshop on Workload Characterization, Austin, Texas, November 2002.
  17. Code Layout Optimizations for Transaction Processing Workloads. Alex Ramirez, Luiz André Barroso, Kourosh Gharachorloo, Robert Cohn, Josep Larriba-Pey, P. Geoffrey Lowney, and Mateo Valero. In Proceedings of the 28th ACM International Symposium on Computer Architecture, Goteborg, Sweden, June 2001.
  18. Managing Complexity in the Piranha Server-Class Processor Design. Robert Stets, Luiz André Barroso, Kourosh Gharachorloo, and Ravishankar Mosur. Workshop on Complexity Effective Design (held as part of ISCA 2001), invited paper, Goteborg, Sweden, June 2001.
  19. Piranha: Exploiting Single-Chip Multiprocessing. Luiz André Barroso, Kourosh Gharachorloo, Tom Heynemann, Dan Joyce, David Lowell, Harland Maxwell, Joel McCormack, Ravishankar Mosur, Jeff Sprouse, Robert Stets, and Scott Smith. IEEE Computer Magazine, April 2001.
  20. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. Luiz André Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese. In Proceedings of the 27th ACM International Symposium on Computer Architecture. Vancouver, CA, June 2000.
  21. Efficient ECC-Based Directory Implementations for Scalable Multiprocessors. Kourosh Gharachorloo, Luiz André Barroso, and Andreas Nowatzyk. In Proceedings of the 12th Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD 2000), São Pedro, Brazil, October 2000.
  22. Impact of Chip-Level Integration on Performance of OLTP Workloads. Luiz André Barroso, Kourosh Gharachorloo, A. Nowatzyk, and B. Verghese. In Proceedings of the 6th IEEE International Symposium on High-Performance Computer Architecture (HPCA-6), Toulouse, France, January 2000.
  23. Performance of Database Workloads on Shared Memory Systems with Out-of-Order Processors. Parthasarathi Ranganathan, Kourosh Gharachorloo, Sarita Adve, and Luiz André Barroso. In Proceedings of the Eighth International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS VIII), San Jose, CA, October 1998.
  24. Memory System Characterization of Commercial Workloads. Luiz André Barroso, Kourosh Gharachorloo, and Edouard Bugnion. In Proceedings of the 25th ACM International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.
  25. An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. Jack Lo, Luiz André. Barroso, Susan Eggers, Kourosh Gharachorloo, Henry Levy, and Sujay Parekh. In Proceedings of the 25th ACM International Symposium on Computer Architecture (ISCA), Barcelona, Spain, June 1998.
  26. Memory System Performance of Commercial Applications. Luiz André Barroso and Kourosh Gharachorloo. Forefront Magazine, Digital Equipment Corporation, June 1997.
  27. Design Options for Small-Scale Shared-Memory Multiprocessors. Luiz André Barroso. Ph.D. Thesis, Department of Electrical Engineering - Systems, University of Southern California, September 1996.
  28. Performance Evaluation of the Slotted-Ring Multiprocessor. Luiz André Barroso and Michel Dubois. IEEE Transactions on Computers, Vol 44, No. 7, July 1995.
  29. RPM: A Rapid Prototyping Engine for Multiprocessor Systems. Luiz André Barroso, Sassan Iman, Jaeheon Jeong, Koray Oner, Krishnan Ramamurthy and Michel Dubois. IEEE Computer Magazine, February 1995.
  30. The Design of RPM: An FPGA-based Multiprocessor Emulator. Koray Oner, Luiz André Barroso, Sassan Iman, Jaeheon Jeong, Krishnan Ramamurthy and Michel Dubois. In Proceedings. of the ACM 3rd International Symposium on Field-Programmable Gate Arrays (FPGA 95), Monterey, CA, February 1995.
  31. The Performance of Cache-Coherent Ring-based Multiprocessors. Luiz André Barroso and Michel Dubois. In Proceedings. of the 20th International Symposium on Computer Architecture, May 1993.
  32. A Methodology for Performance Evaluation of Parallel Applications in Multiprocessors. Daniel Menasce, Luiz André Barroso. Journal of Parallel and Distributed Computing, January 1992.
  33. Scalability Problems in Shared-Memory Multiprocessor Systems. Michel Dubois, Luiz André Barroso, Yang-Sao Chen and Koray Oner. In Proceedings of PARLE 92 (Parallel Architectures and Languages Europe), June 1992.
  34. Delayed Consistency and its Effects on the Miss Rate of Parallel Programs. Michel Dubois, Jin-Chin Wang, Luiz André Barroso, Yang-Sao Chen and Kangwoo Lee. In Proceedings. of the ACM Conference on Supercomputing, November 1991.
  35. Cache Coherence on a Slotted Ring. Luiz André Barroso and Michel Dubois. In Proceedings. of the 20th International Conference on Parallel Processing, St. Charles, Illinois, August 1991.
  36. A Methodology for the Performance Analysis of Parallel Applications in Multiprocessors. Luiz André Barroso. M.S. Thesis, Department of Electrical Engineering, Pontifícia Universidade Católica, Rio de Janeiro, August 1989.
  37. Performance of Processor-Memory Interconnection Networks under Unbalanced Traffic. Luiz André Barroso and Daniel Menasce. Technical Report 084/89, IBM Rio Scientific Center, September 1989.