I am a VP of Engineering of the Geo Platform team and a Google Fellow. My technical interests range from distributed systems software to the design of Google's computing platform. While at Google I have co-authored some well-cited articles on warehouse-scale computing, energy proportionality and storage system reliability. I also co-wrote "The Datacenter as a Computer", the first textbook to describe the architecture of warehouse-scale computing systems, now in its 2nd edition.
I was previously a member of the research staff at Digital Equipment Corporation and Compaq, where our group did some of the pioneering research on modern multi-core architectures. Some of those multi-core processors also use variants of the ring-based cache-coherency interconnects that were the subject of my doctoral research. As a graduate student I was one of the designers of the USC RPM, an early FPGA-based emulator for multiprocessor memory systems.
I am a Fellow of the Association for Computing Machinery (ACM) and the American Association for the Advancement of Science. I was the program chair of ACM ISCA'09 and a National Academy of Engineering Gilbreth Lectureship awardee in 2012. I am currently serving at the National Academies' Computer Science and Telecommunications Board. I have been a keynote speaker at several top-tier research conferences and a guest lecturer at Stanford and PUC-Rio, Brazil.
I hold B.S. and M.S. degrees in Electrical Engineering from the Pontifícia Universidade Católica of Rio de Janeiro, and a Ph.D. in Computer Engineering from the University of Southern California.
I have a limited time budget for external professional activities but have enjoyed many opportunities to work with the academic comunity and other professional organizations.
Serving as a member of the Intelligence Science and Technology Expert Group (ISTEG) of the National Academies of Sciences, Engineering and Medicine
Program chair of ACM ISCA 2009
Serving at the ASPLOS 2016 program committee; having previously served at PCs for ASPLOS'08, ISCA ('01, '02, '05, '06, '07, '09), SBAC-PAD ('01, '03, '06), PACT'04, ICS ('02, '03), IEEE Top Picks in Computer Architecture, 2008.
Serving at the steering committee of the NSF Workshop on Sustainable Data Centers; having previously served on steering committees for ISCA 2010 and ISCA 2011
Lectures at Columbia, Duke, USC, U. Edinburgh, UT Austin, Imperial College, Cambridge University, Harvard University, U. Michigan, UPC, Stanford University, UC Berkeley
Keynote talks at SOCC'16, PLDI'16, FCRC'11, SIGMOD'10, ASPLOS'09, ISLPED'08, IISWC'06, SBAC-PAD'03
National Academy of Engineering's Gilbreth Lectureship, 2012
See list of talks here
As technical lead of the Google Platforms team between 2010-2015, I started a project aimed at hardware acceleration of machine learning applications which resulted in the Tensor Processing Unit (TPU), a custom ASIC that powers several ML systems at Google, including image understanding from Street View.
A short essay on innovation that I wrote for an internal Google audience was subsequently published in Google's re:Work blog. See The Roofshot Manifesto
Co-authored the NRC report: The Future of Computing Performance: Game Over or Next Level?, which describes how underlying circuit technology is no longer yielding the year-over-year improvements we have been accustomed to since Moore's law was "enacted", and what that means to the future of computing.
I wrote the foreword for the 5th edition of Hennessy & Patterson's Computer Architecture: A quantitative approach, the classic textbook on computer architecture which was first printed when I was a graduate student.
Co-wrote the official SIGARCH/TCCA best practices document for ISCA program chairs.
Guest co-editor of IEEE Micro Jul/Aug 2010 special issue on Datacenter-scale Computing
lab at my last name, dot org
1600 Amphitheatre Parkway, Mountain View, CA 94043